MIPs Project with python simulator


In the following are 1.the project guideline 2.ISA and python simulator code 3.4. PRPG program from before 5.whole last project

everything is listed in there. I need a man to hurry up and help me done with the Hardware implement part which is the last jpg in 6 hours, and then I will extend the deadline to give another 24 hours to finish the whole thing.

so target is to finish the whole thing, but I need this Hardware part soon, to be clear

UIC – ECE 366: Computer Organization II – Spring 2019
Project 3: Running PRPG on your own ISA
For this project, you will design your own ISA (Instruction Set Architecture) with its relevant software
and hardware packages. This will be a processor with 8-bit instructions and 8-bit data (registers and
memory), which you will optimize for the PRPG program you have worked on in previous projects,
and showcase your result with a Python simulator.
[ISA Design]
Your ISA design should be very clear with the following:
• a unique name
• which instructions to support, and how to encode each within 8 bits
• registers, general-purpose or specialized
• memory addressing modes: How are addresses of memory constructed / calculated? (This
applies to both data and instruction memory accessing: load/store, and branch instructions).
General specifications:
• Instructions and data are stored in a separate memory hardware (both begin at address 0):
• Instruction memory: 8-bit byte addressable, PC is initialized (automatically) at 0. This memory
should be as large as you need to hold your program (PC might be more than 8 bits if your
program is longer than 256 instructions).
• Data memory: 8-bit byte addressable with the following access limit: for any instruction, it can
either load from or store to (but not both) the data memory exactly 1 byte (8-bits). The data
memory should be able to hold at least 64 bytes. Your program can change the values in the
data memory.
• When implemented, this will be a single-cycle CPU, so each instruction needs to be carried
out by ALU with combinational circuit implementation. If you want to have some special,
“powerful” instruction (such as square), you need to show its implementation in ALU as
combinational logic.
• State any assumptions you make. You can assume that all the registers and data memory bytes
are initialized to be 0, but if any other numbers are needed in the registers, you need to put
them there by some instruction.
Optimization goals:
1. High Speed in SW: (i.e., minimizing dynamic instruction count for one or both programs).
2. Low Cost in HW: (i.e., making your CPU’s hardware design simplified).
[Hardware implementation]
You should provide the detailed hardware implementation for the ISA design, including:
CPU Datapath design. A schematic including register file, ALU, PC logic, and memory
components (see textbook ch 7.3.1).
Control logic design. Decoder truth-table indicating how each control signal is generated for
each instruction (see textbook ch 7.3.2).
ALU schematic. A hierarchical sketch of your Arithmetic Logic Unit which implements
whatever computation operations that your ISA instructions use (See textbook ch 5.2.4).
[PRPG Program]
You should implement the following PRPG program (square and drop the middle) in the assembly
language and machine code, according to the instructions supported by your own ISA:
Part A):
Your program should begin with some code that can initialize the seed (S0) with any 8-bit value.
Each Si (8-bit) is squared into a 16-bit Si^2, and then the middle 8 bits are dropped to yield Si+1.
iii. Your program should write a sequence of 16 pseudo-random patterns, S0 – S15, into data memory
location M[8] – M[23]
Part B):
Your program should compute the (numerical, treated as positive) average of S0 – S15, and store
the result in M[24]
(new) Your program should compute the Hamming Weight of S0 – S15, and store all of them in
M[32] – M[47]
iii. Your program should compute the average of all the Hamming Weights, and store the result in
[Python simulator]
Your ISA should be completed with a python simulator to execute your PRPG program (and, of course,
any program that is written according to your ISA instructions).
Your Python simulator should show clearly important information of execution any machine code of
your ISA instructions / programs, including but not limited to: Dynamic Instruction Count, PC,
Register content, Data memory content, and any necessary debugging information. (5pt extra credits
will be given to 1-2 groups with the best output info and formatting for the Python simulator)
Submission Instructions:
While preparing for your submission files, keep in mind it is your responsibility to make all the files
organized, and everything clear.
Individually, upload the following 10 files (separately, not zipped) on Bb:
1. p3_g_x_report.pdf:
a self-contain PDF report of group x
2. p3_g_x_sim.py:
Python simulator code for your ISA
3. p3_g_x_prpg_251.txt:
4. p3_g_x_prpg_sim_out_251.txt:
machine code for PRPG with S0 = 251
Python output for PRPG with S0 = 251
5. p3_g_x_prpg_118.txt:
6. p3_g_x_prpg_sim_out_118.txt:
machine code for PRPG with S0 = 118
Python output for PRPG with S0 = 118
7. p3_g_x_prpg_79.txt:
8. p3_g_x_prpg_sim_out_79.txt:
machine code for PRPG with S0 = 79
Python output for PRPG with S0 = 79
9. p3_g_x_prpg_s0.txt:
10. p3_g_x_prpg_sim_out_s0.txt:
machine code for PRPG with S0 of your choice
Python output for PRPG with S0 of your choice
Late submission policy and penalty:
submission by the end of the day of
Thu (Apr 4th) – due date
Fri (Apr 5th)
Sat (Apr 6th)
Sun (Apr 7th)
Mon (Apr 8th)
late penalty on your total score
PDF Report components:
Activity Log (20pts)
I) Table of group activity – for example:
/ Activity
Week 8, Fri,
Week 9, Sat
10pm, Online
Doc / GitHub
Update /

II) Individual activity list
Achieved / To-Do


discussion of project 2 for all members
ISA brainstorm
homework 3 problem set discussion
Midterm 1 cheat sheet preparation
Specific Python learning
Algorithms for PRPG
Questions to ask about ISA designs
Review of textbook Ch5 and Ch7 for hardware
implementation part
ISA design – which instructions to include
ISA encoding and instruction format
draft of PRPG program
optimize PRPG program
tinkering with special instructions and their hw
Project Content (80pts)
Part A) ISA intro, Q&A (10pts)
Introduction. This should include the name of the architecture, overall philosophy, specific
goals strived for and achieved.
Instruction list / table. Give all the instructions, their formats, opcodes, and an example.
Register design. How many registers are supported? Is there anything special about the
Branch design. What types of branches are supported? How are the target addresses
calculated? What is the maximum branch distance supported?
Data memory addressing modes. What kind of instructions are used to access data memory?
What is the range of addresses that can be accessed with your design?
What would you have done differently if you had 1 more bit for instructions?
How about 1 fewer bit?
What are the most significant advantages of your ISA (with regard to the PRPG program,
hardware implementation, ease of programming, etc)? What are the main limitations? What
are the main compromises that you have done to make things work, rather than perfecting
What have you done towards the goals of low DIC and HW simplification? What could have
been done differently to better optimize for each of the two goals, if to start over?
If you are given a chance to restart this project afresh with 3 weeks’ time, how would your
group have done it differently?
Part B) Hardware implementations (20pts)
1. CPU Datapath design. A schematic including your register file, ALU, PC logic, and memory
components. Clearly mark out all the signal lines, their names, and how many bits for each.
2. Control logic design. Decoder truth-table indicating how each control signal (one per column)
is specified (0, 1, or X) from each instruction (one per row). If you have special instructions or
register design, explain the control signals briefly.
3. ALU schematic. A hierarchical sketch of your Arithmetic Logic Unit which implements
whatever computation that your ISA instructions use.
Part C) Software Package: PRPG Program + Python (50pts):

Up to 10 pts extra credit will be given to group(s) with the lowest overall Dynamic Instruction
In case your PRPG program does not work correctly, showcase 4 different assembly programs
that work correctly, to convince us that your ISA and simulator works on all your instruction. For
each program, explain clearly what it is supposed to do.

(40pts) Showcase your PRPG program with the following seed S0:

S0 = 251
S0 = 118
S0 = 79
Your (non-trivial) choice of S0
For each of the above cases, show the following:
Assembly code (should be easy to read) of your PRPG program. Make sure your assembly
format is either obvious or well described, and that the code is well commented.
Machine code (either in binary or hex) of your PRPG program. This should be the input
to your python simulator.
Screenshots of your Python simulator’s output for your PRPG program. This should
convince people that your ISA + Python package works correctly for your PRPG program.
(10pts) Include your Python simulator code here, well commented / annotated so that it’s easy
to see how it is corresponding to your ISA design.
The MIPS has a floating point coprocessor (numbered 1) that operates on single
precision (32-bit) and double precision (64-bit) floating point numbers. This
coprocessor has its own registers, which are numbered $f0-$f31. Because these
registers are only 32-bits wide, two of them are required to hold doubles. To
simplify matters, floating point operations only use even-numbered registersincluding instructions that operate on single floats.
.data 0x1001000C
.word 4
lui $t0,0x1001
lw $a0,0xC($t0)
sw $v1,0x4($t0)
addi $t8, $t8, 1
jal function
add $v1,$s1,$v1
“Result: ”
# Print out the result
beq $a0, $0, f_exit
andi $t9, $a0, 1
beq $t9, $t8, f_odd
#if n=0
#if odd
addi $sp,$sp,-8
# push stack
# store return address
# save n
addi $a0, $a0, -1
jal function
mul $v1, $v1, 2
# reload 1st operand
addi $a0, $a0, -2
jal function
j exit
# restore return address
# restore n
addi $sp,$sp,-8
addi $a0, $a0, -1
jal function
mul $v1,$v1,3
addi $s1, $v1, 1
# push stack
# store return address
# save n
# reload 1st operand
# restore return address
j exit
addi $v1,$v1,2
jr $ra
# restore n

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